Dr. Peiyi Zhao
- Office Location:
- Von Neumann Hall 115 and Hashinger Science Center 418
- Zhejiang University, Bachelor of Science
The University of Louisiana At Lafayette, Ph.D.
Dr. Zhao's research interests center around the low power consumption of Digital Integrated Circuits in chip design. Special projects under investigation include flip-flop design, clock gating design, leakage reduction design, ultra-low power design.
low power digital integrated circuits, flip-flop, leakage, clock gating, sub-threshold
- Recent Creative, Scholarly Work and Publications
G. Hang, Y. Yang, P. Zhao, X.Hu, X. You, “A Clocked Differential Switch Logic Using Floating-Gate MOS Transistors,” IEEE the10th International Conference on ASICON, Oct. 28-31, 2013, Shenzhen, China.
G. Hang , H.Zhu, P. Zhao, X.Zhou, “Adjustable Schmitt triggers using floating-gate MOS transistors” IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Oct. 29 -Nov. 1, 2012, Xi’an, China.
G. Hang, P. Zhao, “Novel CMOS Schmitt triggers using floating-gate MOS transistors”, IEEE International ASICON Conference, Oct.25-28, 2011, Xiamen, China
P. Zhao, Jason McNeely, Weidong Kuang, Zhongfeng Wang, “Design of Sequential Elements for Low Power Clocking System” IEEE Transacting on Very Large Scale Integration (VLSI) system, vol. 19, no.5, pp. 914 – 918, May 2011.
P.Zhao, Z.Wang,G. Hang, “Power Optimization for VLSI Circuits and Systems,” IEEE 10th International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2010), Nov.1-4, Shanghai, China(Invited talk, Session chair, TPC member).
W. Kuang, P. Zhao, J.S.Yuan, and R. DeMara, “Design of asynchronous circuits for high soft error tolerance in deep submicron CMOS circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.18, no.3, pp.410-422, March 2010
P. Zhao, J. McNeely, S. Venigalla, G. P. Kumar, N.Wang, M. Bayoumi, W. Kuang, and L. Downey, “Low Power Clocked-Pseudo-NMOS Flip-flops for Level Conversion in Dual Supply Systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 17, Issue 9, pp.1196 – 1202, Sept. 2009.
P. Zhao, J. McNeely, Pradeep Golconda, Magdy A. Bayoumi, Bob Barcenas, Jianping Hu, “Low Power Design of Double-Edge Triggered Flip-Flop by Reducing the Number of Clocked Transistors,” IEEE International Conference on Circuits & Systems for Communications(ICCSC08), May 26-28, 2008, Shanghai, China.
P. Zhao, J. McNeely, G. P. Kumar and M. Bayoumi, “Low Power Keeper for High Fan-In Domino Circuits,” in IEEE International Symposium on Circuits and Systems(ISCAS 2007), May 27-30, 2007, New Orleans, LA.
P. Zhao, Jason McNeely, Pradeep Golconda, Magdy A. Bayoumi, Kuang W.D, and Bob Barcenas, “Low Power Clock Branch Sharing Double-Edge Triggered Flip-Flop,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems,Vol.15, No.3, March 2007.
Md Faisal, P. Zhao, M. Bayoumi, “A Low-Power Clock Frequency Multiplier,” IEEE International Symposium on Circuits and Systems(ISCAS 2006), May 21-24, 2006, Kos, Greece.
P. Zhao, G. P. Kumar, Jason M. and M. Bayoumi, “External- Internal Dual Switch Leakage Controlled Flip-flop design,” IEEE International Mid West Symposium on Circuits and Systems(MWSCAS 2005), August 10, 2005, Cincinnati, Ohio.
P. Zhao, G. P. Kumar and M. Bayoumi, “Contention Reduced/Conditional Discharge Flip-Flops for Level Conversion in CVS Systems,” IEEE International Symposium on Circuits and Systems (ISCAS 2004), May 23-26, 2004, Vancouver, British Columbia, Canada.
P. Zhao, G. P. Kumar, A. Chidanandan and M. Bayoumi, “A Double-Edge Implicit-Pulsed Level Convert Flip-Flop,” IEEE Computer Society Symposium on VLSI (ISVLSI04), February 19-20, 2004, Lafayette, Louisiana, pp. 141-144. (Presentation acceptance rate: 23%).
P. Zhao, T. Darwish, M. Bayoumi, “High Performance and Low Power Conditional Discharge Flip-Flop,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol 12., No. 5, pp. 477-484, May 2004. Cited by 11 papers.
P. Zhao,T.Darwash, and M. Bayoumi, “Low Power Conditional-Execution Pulsed Flip-Flop,” IEEE Computer Society, Looking Forward Magazine, Summer 2003.
P. Zhao, T. Darwish, M. Bayoumi, “Low Power and High Speed Explicit-Pulsed Flip-Flops,” 45th IEEE International Midwest Symposium on Circuits and Systems Conference (MWSCAS02), Tulsa, Oklahoma, August 4-7, 2002, vol.2, pp.477-480.