Cadence University Program Member

» Cadence Design Systems Software Used at Chapman University

Cadence is a premier developer of integrated circuit CAD (computer aided design) tools. The company was established in 1988 and currently has over 5,000 employees. The world headquarters is located in San Jose, CA.

Some of the Cadence software tools that student typically come into contact with include Custom IC (Design Environment, Design Entry, Circuit Simulation, Physical Verification, Pcell Generator), Digital IC.

+ - Courses and Research Using Cadence Tools

Currently the Cadence tools are used in the following courses:

  • CPSC330 -- Digital Logic Design I
  • CPSC366 -- Digital Logic Design II
  • CPSC 465 -- Integrated Circuit Design I
  • CPSC 466 -- Integrated Circuit Design II
  • CPSC 351 -- Computer Architecture I

Currently the Cadence tools are used in the following research projects:

  • Low energy, low power clocking circuits design, clock gating, low leakage circuits
  • Ultra low energy, low power circuits
  • Radiation hardening circuit

+ - The Custom IC Bundle Software Reference List

Design Environment

Virtuoso® Simulation Environment 206 IC617
Virtuoso® AMS Designer Environment 70000 IC617
Virtuoso® Analog Design Environment – XL 95210 IC617
Virtuoso® Analog Design Environment – GXL 95220 IC617
Virtuoso® Visualization & Analysis XL 95255 IC617
Virtuoso® Implementation Aware Design Option 95510 IC617
Virtuoso® Layout Suite EAD 95600 IC617
Virtuoso® EAD 3D Precision Solver 95610 IC617
Virtuoso® EAD Advanced Electrical Analysis 95620 IC617
Virtuoso® LDE analyzer Option 95230 MVS152

Design Entry

Cadence® SKILL Development Environment 900 IC617
Virtuoso® Schematic VHDL Interface 21060 IC617
Virtuoso® Schematic Editor Verilog Interface 21400 IC617
Virtuoso® Schematic Editor – XL 95115 IC617
Virtuoso® Analog Oasis Run-Time Option 32100 IC617
Cadence® OASIS for RFDE 32101 IC617

Circuit Simulation

Virtuoso® Schematic Editor HSPICE Interface1 276 IC617
1 requires additional licenses that must be obtained from Synopsys
Virtuoso® Analog HSPICE Interface Option1 32760 IC617
Virtuoso® Multi-mode Simulation Power Option 91400 MMSIM151
Virtuoso® Multi-mode Simulation CPU Accelerator option 91500 MMSIM151
Virtuoso® RelXpert 33580 MMSIM151
Virtuoso® Multi-mode Simulation with Spectre XPS 90004 MMSIM151
Spectre Extensive Partitioned Simulator 91600 MMSIM151
Spectre Characterization Simulator Option 3500 MMSIM151

Interfaces

Virtuoso® EDIF 200 Reader 940 IC617
Virtuoso® EDIF 200 Writer 945 IC617
Cadence® Design Framework Integrator’s Toolkit 12141 IC617

Physical Verification

Dracula® Graphical User Interface 365 IC617
Dracula® Physical Verification and Extractor Suite 70520 IC617
Diva® Physical Verification and Extractor Suite 71520 IC617
Assura™ Design Rule Checker 72110 ASSURA41
Assura™ Layout vs. Schematic Verifier 72120 ASSURA41
Assura™ Graphical User Interface Option 72140 ASSURA41
Assura™ Multiprocessor Option 72150 ASSURA41
Virtuoso® Quantus QRC Extraction - XL QRCX300 EXT151
Virtuoso® Quantus QRC Advanced Analysis GXL option QRCX310 EXT151
Cadence® Quantus QRC Advanced Modeling GXL Option QRCX320 EXT151
Cadence® Quantus QRC Display Technology Option QRCX330 EXT151
Cadence® Quantus QRC Advanced Modeling20 GXL Option QRCX520 EXT151
Cadence® Quantus QRC Advanced Node Modeling Option QRCX530 EXT151
Cadence® QuickView Layout and Mask Data Viewer K2200 PVS151
Cadence® QuickView Sign-off Data Analysis Environment K2211 PVS151
Cadence® Physical Verification System Design Rule Checker XL 96210 PVS151
Cadence® Physical Verification System Layout vs. Schematic Checker XL 96220 PVS151
Cadence® Physical Verification System Programmable Electrical Checker 96230 PVS151
Cadence® Physical Verification System Programmable Electrical Checker XL 96235 PVS151
Cadence® Physical Verification System Results Manager 96240 PVS151
Cadence® Physical Verification System Design Analysis Option 96245 PVS151
Cadence® Physical Verification System QuickView Signoff Environment 96246 PVS151
Cadence® Physical Verification System Constraint Validator 96300 PVS151
Cadence® Physical Verification System Constraint Validator XL 96305 PVS151
Cadence® Physical Verification System Advanced Device Option 96330 PVS151
Cadence® Physical Verification System Advanced Analysis Option 96320 PVS151
Cadence® Physical Verification System Mask Rule Check Option 96350 PVS151
Virtuoso® Integrated Physical Verification System Option for Layout Suite 96400 PVS151

Pcell Generator PASPCG PAS31

Graphical Technology Editor PASGTE PAS31
Generator for Assura™ compatible verification decks PASASG PAS31
Generator for Diva® compatible verification decks PASDIG PAS31
Error Cell Generator PASECG PAS31

+ - Digital Integrated Circuits Bundle

Place & Route and Timing
Virtuoso® Layout Suite - GXL1 95321 IC617
Virtuoso® DFM Option 95311 IC617

Cadence is a registered trademark of Cadence Design Systems, Inc

Date last updated: June 25, 2016

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